A FPGA Implementation of High Security Hybrid Reconfigurable Cryptographic Processor with RSA and SEA

Data security is in Demand in everyday life of Digital World, since Digital data’s can be reproduced much easily. To achieve the maximum security required a Parallel Processing, User Reconfigurable Cryptographic RISC Microprocessor is proposed in our paper. Rather than protecting the data using tools and external codes, a microprocessor is specially designed in our project to offer maximum digital security. Cryptographic processor can be classified either as asymmetric cryptography or a symmetric cryptography processor. Asymmetric cryptography has the advantage of Reception security but has the limitation of High resource Utilization. And a symmetric cryptography processor has the limitation of single key security but comparatively has the advantages of low area, resource and power consumption. Thus in this project we are proposing Hybrid architecture in which both the advantage of asymmetric and symmetric cryptographies are combined. For implementation, Asymmetric RSA cryptography and a symmetric lightweight SEA encryption is combined to mutate a reconfigurable Cryptographic processor. Index wordsData security, Reduced instruction set Computer (RISC), Reconfigurable Architecture, Cryptographic Processor, Scalable Encryption Algorithm (SEA), Rivest-Shamir-Adelman (RSA) cryptosystem. -----------------------------------------